The trend in high performance computers is to use increasing numbers of processors operating common memory modules referred to sometimes as Basic Storage Modules (BSM). The coupling between these processors and common memory modules is by some form of network. The coupling can be tightly coupled or loosely coupled. IBM Corporation System/390.TM. 9000 Series (System/390 is a trademark of International Business Machines Corporation) family is an example of a tightly coupled multi-processor system. In a tightly coupled system the processors share real storage, are controlled by the same control program, and can communicate directly with each other. In a tightly coupled system there may be N processors and M BSMs. All processors have equal access to a BSM through some form of N.times.M switch, such as a cross-bar switch to select the path between a given processor and a currently addressed memory for storing and fetching data. In loosely coupled systems the processors share access to direct access storage and are coupled, for example, by channel to channel adapters for passing control information. This present invention is most suitable for tightly coupled applications.
The performance parameters of most importance to the system are the processor cycle time, bandwith, electrical path length, round trip delay and timing skew. The cycle time is minimized by placing the cycle determining path elements in the closest possible proximity to each other. The bandwidth between processor and memory is achieved by using the fastest data rate over a large number of parallel connections between processors and switches and between switches and BSMs. The electrical path length is the length between data latching points on different, but interconnected, functional units as measured in nanoseconds. The total round trip delay from a processor to a memory and back is known as the memory latency. The skew is the electrical path length differences due to variations in routing from one point to another.
Applicant's U.S. Pat. No. 5,058,053 shows one system for providing some of these parameters of importance in a system with unidirectional information flow through the memory modules. Applicant has other pending applications with plural memory modules, BSMs and request and response switches. They are: U.S. application Ser. No. 07/675,583 filed Mar. 26, 1991 entitled "High Performance Computer System Package" and U.S. application Ser. No. 07/675,243 filed Mar. 26, 1991 entitled "Integrated Circuit Chip Package Having Signal Input/Output Connections Located at Edges of the Substrate," now U.S. Pat. No. 5,168,347. These applications are incorporated herein by reference. This present invention provides shorter path lengths between processors and BSMs.